Technology radar
The Czech National Semiconductor Cluster (CNSC) promotes the development of the Czech and European semiconductor ecosystem — across design, power electronics, advanced packaging and the convergence of microelectronics with the energy, mobility and connectivity sectors. CNSC and its members are committed to strengthening Europe's technological sovereignty, security of supply and competitiveness, while ensuring that Czech industry and research take an active part in the EU's semiconductor initiatives.
The current period is defined by numerous and fast-moving technological developments and possible disruptions, particularly at the intersection of microelectronics, artificial intelligence and energy. These transformations have a significant impact on the European semiconductor ecosystem and on the EU funding instruments designed to support it. Stakeholders must therefore prepare, which sometimes imposes difficult choices about which technologies to prioritise.
This Technology Radar evaluates semiconductor topics that have a potential impact on the European ecosystem and on Czech participation in it. Its objectives are:
- Early identification of new technologies, technological trends and potential disruptions in the semiconductor value chain;
- Increased awareness of the opportunities and threats associated with emerging developments, and of the EU instruments able to fund them;
- Stimulation of innovation by combining each technology with an assessment of its strategic and funding potential.
For each trend, a fact sheet summarises the key elements of the technology, its maturity, its impact on the European ecosystem, and — distinctively for this radar — the EU instruments through which it can be financed: IPCEI ME, IPCEI ME/CT, IPCEI AST, the Chips Act and the proposed Chips Act 2.0.
An aggregated view of all trends is constructed by positioning each technology on a diagram according to estimates of time to industrial maturity (horizontal axis) and magnitude of impact on the EU semiconductor ecosystem (vertical axis). It should be noted that the position of each technology is indicative and could be the subject of endless debate — in particular for technologies such as AI accelerators, which are already widely used yet subject to potentially disruptive new developments.
The trends analysed cover power electronics (SiC/GaN), compute and edge AI, manufacturing and pilot lines, next-generation connectivity, materials and advanced packaging, and the design and EDA-tools layer (the Chips Design Platform). Each technology is mapped to the EU instrument best suited to carry it from research to first industrial deployment, with particular attention to the convergence fields relevant to a proposed Czech specialised pilot line.
The radar is further grounded in a survey of European semiconductor Competence Centres (25 responses from 23 countries, May 2026), in which each centre rated 26 technology domains on a four-level scale — Main focus / pioneer, Secondary / supporting, Emerging / experimental, or Not applicable — and described its technology priorities for the next 3–5 years, main challenges, and preferred areas of cross-centre cooperation. The survey signal is reflected in the technology fact sheets (where a domain is a current strength or an emerging trend across centres) and analysed in full under the Competence centres tab. Given the rapid evolution of both technologies and the EU policy framework, the radar is intended to be updated regularly.
Click any technology to open its fact sheet and see which EU instruments can fund it. Use the filters to isolate a sector. Horizontal axis = time to industrial maturity; vertical axis = magnitude of impact on the EU semiconductor ecosystem.
The EU instruments
Five instruments form a continuum: the two earlier IPCEIs built the base, the Chips Act created the pilot-line and design infrastructure, IPCEI AST funds the next disruptive wave, and Chips Act 2.0 reframes the policy around demand and sovereignty.
Technology × instrument matrix
Which instrument can carry which technology. A technology can map to several instruments — e.g. SiC sits in ME/CT today and in AST for next-generation 300 mm device work.
| Technology | Sector | Eligible instruments |
|---|
Where the Czech / CNSC pilot-line concept fits
The proposed convergence pilot line — energy-grid AI, SiC/GaN power electronics, advanced MCUs, Edge AI and next-generation communications — maps cleanly onto IPCEI AST fields (power electronics & energy saving, AI chips/accelerators, sensors) and onto Chips Act Pillar I continuity (design platform, competence centres). Chips Act 2.0's demand-side and sovereignty emphasis strengthens the case for a specialised — rather than leading-edge — facility.
Results of a survey of European semiconductor Competence Centres (May 2026) used to ground the radar in observed capability. Each centre rated 26 technology domains on a four-level scale and described its forward priorities, challenges and cooperation needs. The European Network of Chips Competence Centres (ENCCC) is coordinated by the aCCCess project — a four-year Coordination & Support Action under the EU Chips Act, launched March 2025, connecting the competence centres with pilot lines and the design platform. CNSC is a partner in aCCCess (piloting AI tools for competence centres and sharing semiconductor-ecosystem best practices).
Ask ChiCC — the aCCCess assistant
ChiCC is the aCCCess network's AI chatbot. It helps companies, SMEs and start-ups navigate the European Network of Chips Competence Centres — finding the right centre, pilot line, design-platform service or funding route.
Open on acccess.euTechnology-domain coverage across centres
Technology-domain radar
The same data as a radar. Each spoke is a domain; the distance from the centre is a weighted strength score across the 25 centres (main focus = 3, secondary = 2, emerging = 1, divided by the maximum). The further out, the stronger that domain is across the European network.
IPCEI readiness signals
How prepared the network is to feed into IPCEI-type instruments — read from international-cooperation experience, EU-network membership, and which funding programmes the centres already use or promote. Counts out of 25 centres.
Government & public-funding services offered
The public-facing services centres provide — the front-office function that makes them an entry point to EU and national funding. Counts out of 25 centres.
Trends detected — what the survey signals
Reading the ratings together with the free-text priorities for the next 3–5 years, four patterns stand out:
Stated technology priorities (next 3–5 years)
Most frequently named themes across the open responses:
Main challenges reported
Where cross-centre cooperation would help most
Reading for the CNSC pilot-line case
Power electronics, chip design, photonics and advanced packaging emerge as established European strengths, while the most-named forward priorities — photonics, quantum, advanced packaging / heterogeneous integration, wide-bandgap power and edge / AI-driven design — overlap almost exactly with the convergence fields of the proposed Czech pilot line and with IPCEI AST. The dominant challenges (funding sustainability, SME outreach, skills) and the strong demand for access to pilot lines and the Chips Design Platform reinforce the rationale for a specialised, access-oriented Czech facility rather than a leading-edge fab.
Pillar I of the EU Chips Act — design enablement & EuroCDP
Pillar I ("Chips for Europe") builds Europe's capacity to design and prototype chips. Its design-enablement layer runs through the EU Chips Design Platform (EuroCDP) and a distributed network of Design Enablement Teams (DETs) — the operational route by which start-ups and SMEs reach pilot lines and foundries. This is the continuity the CNSC position paper defends.
What sits inside Pillar I
Context: ~30% of global IC start-ups are hosted in Europe, yet they attract only ~6% of global start-up funding — the bottleneck is access to venture infrastructure, not talent. Design is ~33% of the semiconductor value chain.
Pillar I pilot lines — competences
Five pilot lines bring chip technology "from lab to fab", together ~€3.7 bn of combined EU and national investment. Each carries a distinct competence; DETs and EuroCDP users reach them through the design platform.
Additional Chips JU lines and projects referenced in the DET decks and Commission communications: SPINS (spintronics), 2DPL (2D materials), P4Q / quantum pilots, and STARLight (300 mm silicon photonics).
EuroCDP — the EU Chips Design Platform
eurocdp.euAn integrated platform offering essential design services in one place, to grow EU fabless market share by lowering technical and cost barriers and encouraging VC funding. Coordinated by imec; the Platform Coordination Team includes ČVUT (Czech Republic). A EuroCDP grant covers 35% of eligible project costs; access is limited to entities established in Chips JU Participating States (with conditional access for OECD/Mercosur-controlled entities on EU-added-value, economic-security and sovereignty criteria).
User journey through the platform
DET capabilities — technology coverage
The nine DETs' combined process-technology coverage. ● available · ◐ in development.
DET capabilities — design expertise & pilot-line access
Pilot lines referenced: APECS (packaging), FAMES (FD-SOI), NanoIC, PIXEurope (photonics), WBG (wide-bandgap), plus SPINS and 2DPL. Foundry access spans GlobalFoundries, STMicroelectronics, TSMC, X-FAB, IHP, Samsung, Intel and specialised photonic foundries.
Why this matters for the CNSC position paper
EuroCDP and the DET network are the concrete delivery mechanism of Pillar I continuity the paper argues to preserve under Chips Act 2.0. The DETs' technology coverage — wide-bandgap (GaN/SiC), FD-SOI/RF, photonics, mixed-signal and emerging quantum — maps directly onto the proposed Czech convergence pilot line and onto IPCEI AST fields. A Czech specialised facility positioned as an access point into this network (a future DET or pilot-line node) would reinforce the design-platform layer the survey shows centres most want to share.
Czech semiconductor centres
The national building blocks implementing the Czech National Semiconductor Strategy (NPS, 2024–2029) and connecting Czechia to the EU Chips Act. Together they cover the design platform layer (Pillar I), Taiwan academic cooperation, and applied R&D from raw materials to integrated devices.
National Semiconductor Strategy of the Czech Republic (NPS)
mpo.gov.czApproved by the Czech government on 10 October 2024, the National Semiconductor Strategy is the umbrella framework all the centres above implement. Building directly on the EU Chips Act, it is led by the Ministry of Industry and Trade (MPO) with the Government Office and the Ministry of Education, and was shaped in close cooperation with CNSC. It sets a headline goal of tripling the size of the Czech semiconductor sector and reaching 9,000 specialists by 2029, organised into five strategic areas: R&D and innovation, export support, human capital and skills, attracting investment, and improving business conditions.
First concrete measures: establishing the national competence centre (CSC), joining the Chips Act pilot-line programme, IPCEI ME/CT participation, and a CzechInvest task force for foreign opportunities. The NPS is the document the CNSC position paper proposes to upgrade alongside the Chips Act 2.0 response.
How they fit together
The Czech Semiconductor Centre is Czechia's node in the EU Chips Act Pillar I network (and connects via aCCCess to the EuroCDP design platform). ACDRC adds the Taiwan academic-cooperation and chip-design-education dimension. Semiconductors4All (TA ČR) funds applied R&D across the value chain under the National Strategy. CNSC (Šumavská 416/15, Brno) is the connecting industrial platform across all of them — and a partner in aCCCess and a member of the CSC consortium. This is the concrete national base the CNSC position paper builds on.
CNSC Radar — Czech semiconductor value chain
A competence map of the Czech semiconductor value chain, built from an analysis of the ~50 members of the Czech National Semiconductor Cluster (CNSC). It shows where Czech industry, universities and research institutes are positioned along the chain — from design and materials through equipment, fabrication and packaging to metrology and systems. This is the national capability base the CNSC position paper draws on.
Value-chain coverage at a glance
Member organisations grouped by their primary role in the chain. The Czech strengths — design/IP, metrology & electron microscopy, and a broad academic base — stand out clearly.
Based on public member profiles (semicz.cz). Several members appear in more than one stage where they span the chain — e.g. MycroftMind (design + energy grid) and Smarter Instruments (metrology + energy/power test + government services / IPCEI & Chips Act guidance). Each member name links to its website.
Competence by value-chain stage
Representative members per stage, with their core competence.
What the map shows
The Czech value chain is design-heavy and analysis-heavy: Brno hosts the strongest EU RISC-V and EDA ecosystem (Codasip, ASICentrum, Tropic Square, Analog Bits) and roughly a third of the world’s electron-microscopy production (Thermo Fisher, Tescan, Delong). A 2026 milestone deepened this: onsemi acquired Codasip’s RISC-V / energy-efficient processor division (including Codasip Studio), expanding its Brno design centre across RISC-V processors, mixed-signal ASICs and sensing, while Codasip refocused on CHERI cyber-resilient SoCs — a sign that Czech design IP now scales into global industry. Front-end fabrication is anchored by onsemi and NXP in Rožnov (power / SiC and mixed-signal), supported by a deep equipment and materials supply chain (SVCS, Edwards, Crytur, EP Rožnov). A distinctive Czech angle is the energy-grid & power convergence — MycroftMind’s embedded grid AI, Smarter Instruments’ power/SiC test equipment and Hitachi Energy’s grid power devices — which maps directly onto the proposed Czech specialised pilot line. The thinner links — advanced packaging, dedicated test and wide-bandgap volume — are exactly where that pilot line and the Chips Act 2.0 response can add the most value.
Semiconductors4All — project portfolio
The applied-R&D project portfolio of Semiconductors4All (TA ČR grant TQ28000004), one of the centres delivering the National Semiconductor Strategy. 17 projects across the Czech chain — power, sensors, microscopy, manufacturing and ICT — coordinated by Brno University of Technology with industry and academic partners.
Portfolio at a glance
IPCEI AST — German participant landscape
Active participating companies in the German IPCEI on Microelectronics & Communication Technologies (IPCEI AST — Advanced Semiconductor Technologies chain), grouped by role in the value chain. This is the German national cohort — a reference for how a large Member State organises its IPCEI participation, and a map of potential partners for Czech projects.
At a glance
Instrument timeline
How the EU semiconductor funding architecture has evolved — and where it is heading.
Version & changelog
Send feedbackThis is a living working draft. Feedback is welcome at info@semicz.cz — please note the tab/section, what to add/fix/remove, and a source if you have one.